Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Sean Kelly
Date : Tue Aug 30 2005 02:12 pm

Alexander Terekhov wrote:
> Sean Kelly wrote:
> >
> > So am I correct in concluding that, at a program level, loads and
> > stores (from a single CPU) appear to occur in program order for all x86
> > processors?
>
> Well, not quite. Under PC you may still need a store-load fence.

Ah, that makes sense.  So loads can be migrated upwards above preceding
stores.  And the only applicable fence for x86 is LOCK (which is a full
fence).  Seems simple enough.


Sean

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