Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : Michael Pryhodko
Date : Mon Apr 04 2005 09:21 pm

> > Hmm... Wait a second, I thought that sfence is placed on pipeline
just
> > like any other instruction and when it is retired -- it simply
flushes
> > store buffers (plus maybe something to do with cache coherency
> > mechanism). In that case if anything lies on pipeline behind sfence
--
> > it will be there, nobody will remove it. Or maybe I am wrong and it
is
> > processed completely in another way, for example:
> > whenever sfence fetched from memory, pipeline is flushed, store
buffers
> > flushed, sfence immediately retired and continue as usual.
>
>     Think about what you're saying. What happens if an instruction
after the
> sfence does a store and that store has already been put in the
buffer?
> Flushing the buffer will flush the wrong stores. (Modern x86 CPUs get
much
> of their speed from out-of-order execution.)

And by the way -- I don't think that out-of-order executed 'store' gets
to store buffer before instruction retired by ROB. Because every
interrupt flushes/drains store buffers. Definitely out-of-order
execution does not work as you think it works.

Bye.
Sincerely yours, Michael.

.