Subj : Re: System To : Brian Hall From : Tony Ingenoso Date : Wed Mar 07 2001 06:50 pm From: "Tony Ingenoso" 8K "D" cache + the micro-ops "I" cache. This scheme is sort of like the original P5's 8K I and 8K D caches. L2 is full speed though and has huge cache line - 128 bytes. With today's bloatware OOP crap the effectivness of L1 has dropped considerably except under very specialized circumstances. The L1 mattered when apps and OS's were still somewhat tight, K6 and Centaur C6's 64K L1 shined then when things fit in them. Nothing fits in them anymore :-( "Brian Hall" wrote in message news:3aa71d28$1@w3.nls.net... > > Intel screwed up when they reduced the size of the L1 cache. 8K? What > were they thinking? > > Brian --- BBBS/NT v4.00 MP * Origin: Barktopia Gating Project http://HarborWebs.com:8081 (1:379/45) .