Subj : Re: hyperthreading in database-benchmarks
To   : comp.arch,comp.programming.threads
From : David Kanter
Date : Wed Oct 12 2005 10:46 pm


Bill Todd wrote:
> Oliver S. wrote:
> > Has anyone found information on how much hyperthreading is able to
> > improve the
> > performance of database-workloads (OTP as well as DWH)?
>
> My recollection is that POWER5's SMT is said to give it something like a
> 35% boost in TPC-C, and Montecito's coarser-grained 'hyperthreading' is
> said to provide less (more like 25%).  Those of course are both
> dual-thread SMT implementations without any more execution units than
> their non-SMT predecessors:  EV8's quad-thread implementation did (IIRC)
> contain more execution units, was fine-grained, and was said to provide
> over 2x (possibly as much as 3x - it's been a long time since I visited
> the material) the TPC-C throughput that a non-SMT version would have
> managed.

The EV8 had quite a few more functional units than anything shipping
today, see Paul DeMone's article:
http://www.realworldtech.com/page.cfm?ArticleID=RWT021802145442&p=2

8 ALUs
4 FPUs
2 LD units
2 ST units

It was estimated by Joel Emer at about a 225-230% boost (hard to tell
with the graph and scale):

www.cs.washington.edu/research/smt/papers/compaqMF.ppt

This persuades me that a chip designed for SMT from the ground up can
get quite a bit better than just 40%.  The real question is whether you
are better off with CMP than a wide SMT...hard to say and we'll
probably never know.

David

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