Subj : Re: transactional memory question
To   : comp.arch,comp.programming.threads
From : kimo
Date : Tue Oct 04 2005 12:37 am

Ravi Rajwar is an advocate of Hardware based Transactional memory - for
a bibliography of Academic papers - he'll be the person that will know
the state of the art:
http://www.cs.wisc.edu/trans-memory/biblio/index.html


Not listed yet in the above bibliography , I thought this new paper
from Sun was fascinating and simple ideas for future Hardware TM
support - but it's not an entirely fleshed out solution yet - but you
can see they are trying to get away from CAS and LLSC operations as
well -

http://research.sun.com/techrep/2005/smli_tr-2005-132.pdf

Particularly, I wondered if it could be used in conjunction with
Intel's promotion of Fully Buffered DIMMS:

http://www.theinquirer.net/?article=15167

====================

Tim Harris now from Microsoft seems to be leading the charge for some
innovative approaches to Software TM.  Some say that it's too soon to
put stuff into hardware, that we need to figure out the best way to
model TM in software first (assuming TM is the best approach for
concurrency).

This particular paper on Composable Memory Transactions is quite
interesting:
http://research.microsoft.com/Users/simonpj/papers/stm/stm.pdf


He's also leading a conference this month that is generating a lot of
excitement:
http://research.microsoft.com/%7Etharris/scool/

Lastly, i have found some of the observations in this IBM Technical
report regarding Atomic Sets and Concurrency - a helpful new theory
(with proofs!) approach for modeling concurrency in languages - to be
published in POPL'06.

http://www.research.ibm.com/people/m/mvaziri/papers/atomicsets.pdf


(from Sun paper)
"We introduce Transient Blocking Synchronization (TBS), a new approach
to hardware synchronization for mega-scale distributed-memory
multiprocessor machines. Such machines, with thousands of processors
and controller based memory modules, ar e essentially distributed
networks, and one must search for new paradigms that provide hardware
synchronization support with high levels of robustness and minimal
protocol and communication overhead. It is our claim that the semantics
of non-blocking synchronization primitives such as Compare&Swap and
LoadLinked/StoreConditional on the one hand, and blocking ones such as
Full/Empty-bits on the other, will introduce high communication and
space costs when implemented on large scale machines.

TBS is a novel hardware synchronization paradigm resting between the
classic blocking and non-blocking approaches to synchronization. It is
an example of how, based on very weak ''transient'' hardware
blocking, that is, blocking that may be revoked at any time, one can
provide non-blocking universal synchronization with low communication
and space complexity. This paper presents a set of simple TBS
single-location synchronization operations and shows that they provide
low cost non-blocking emulations of all known read-modify-write
operations.  Moreover, it shows that the combination of TBS with
hardware supported transactional bits, a variation on traditional
hardware full/empty bits, can provide low message cost implementations
of multi-word transactional operations."

.