Subj : SMP-dreams ...
To   : comp.programming.threads
From : Oliver S.
Date : Tue Sep 27 2005 07:28 pm

I thought about upcoming processors which will have a lot of cores
and came to the idea, that this may will emphasize the importance of
lock-free techniques a bit (although I must say that lock-free tech-
niques are not that important like it looks like for some of the lock
-free-protagonits here).
So I had the idea that future CPUs should implement an atomic CAS
-operation whith operands that have the lenght of a whole cache-line.
The execution resources for such an operation would be preferrably
placed in the cache-controller.
And because of the issues with deallocating items in lock-free struc-
tures (I know that this can also be solved with garbage-collection
mechanisms), I had the idea, that an architecture may provide vari-
ants of load and store instructions that don't produce a page-fault
on unallocated pages, but just set a flag (f.e. the zero-flag) to
indicate that a load couldn't be performed.

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