Subj : Sun's Niagara MTA-architecture
To   : comp.programming.threads
From : Oliver S.
Date : Sun Sep 25 2005 06:51 pm

I've recently read an article on Ace's Hardware about Sun's upcoming
Niagara-CPU ([1]). There's a lot of speculation and vage sophistry in
this article but this are the facts about this CPU:

- Ultra-Sparc compatible architecture
- eight cores with each 32kB data-cache and 64kB instruction-cache
- 3MB L2-cache
- each core is a simple in-order core with can execute one
  instruction per clock-cycle
- each core swaps to another thread when an instruction stalls,
  f.e. by accessing the L2-cache
- integrated ethernet-controller with tcp/ip offload engine to
  improve tcp/ip-throughput
- unfortunately no SMP-support in the first version
- FP-performance which isn't worth to be mentioned (and even not
  necessary for a server-cpu)
- no branch-predictor in the cores

I think that this is the best way for Sun to go. Sun doesn't seem to
be able to catch up with the single-threading performance of current
x86-cores, but fortunately, the're mainly in the server-market where
single-threaded performance doesn't play a big role; in contrast to
the x86-market where single-threaded performance counts a lot because
most x86-CPUs sold are desktop-CPUs. Thus, designing CPUs with simple
cores like the Niagara-cores isn't adoptable by AMD or Intel.

[1] http://www.aceshardware.com/read.jsp?id=65000292

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