Subj : Re: [.NET] Volatile Fields [correction] To : comp.programming.threads From : David Hopwood Date : Wed Sep 21 2005 09:02 pm Joe Seigh wrote: > David Hopwood wrote: >> Joe Seigh wrote: >> >>> AFAICT, Alexander seems to think the x86 memory model is just PC and >>> *all* of the other stuff in the x86 docs doesn't count. >> >> *Most* of the other stuff in the x86 docs is about non-WB memory types, >> or about what is visible on the system bus, as opposed to what is visible >> to processors. > > "In a single-processor system for memory regions defined as write-back > cacheable, the following ordering rules apply:" Followed by a list of rules, none of which contradict the model for WB memory on x86 being exactly processor consistency. (This list wouldn't be expected to be sufficient to imply processor consistency, since it only considers a single-processor system.) >>> If you want to do global memory barriers just using PC and nothing else, >>> you can. Just use a common memory location to "sync" everything with. >> >> If you don't care about lousy performance due to cache line pinging. > > Lousy performance compared to what? Now that I look at your suggestion more closely, it doesn't appear to work, so its performance is moot. Start with F (fence) == Y == Z == 0. P1: F = 1; Y = 1; P2: if (Y == 1) { (void) F; F = 1; Z = 1; } P3: if (Z == 1) { (void) F; assert(Y == 1); } can fail, e.g. in this execution: P1 -(F=1)-(Y=1)---------------------------------------------------------- \ \ \\______________________________________________ \ \ \ \ P2 -----*-\---*-(Y==1)-(F==1)-(F=1)-(Z=1)------------------- \ ---------- \ \ \ \ \ \ \ \ P3 ----------*---------------------*-----*-(Z==1)-(F==1)-(Y==0)-*-(Y==1)- -- David Hopwood .