Subj : Re: Using hierarchical memory as an acquire memory barrier for dependent loads To : comp.programming.threads,comp.arch From : Seongbae Park Date : Tue Sep 13 2005 09:21 am Nick Maclaren wrote: > In particular, if you make cache and TLB control explicit, an OpenMP Do you really believe that programmers can handle a full explicit control of cache which could very well cause a hang or extreme starvation ? I'm not even sure runtime and compiler writers would be able to handle it very well - that's maybe because I haven't given a lot of thought to it though. Shouldn't they (both general programmers and compiler/runtime writers) be much better off with an "advice" mechanism ? Prefetch is one such advice, and you can easily imagine the reverse of prefetch, and prefetch (and reverse) for TLB as well. > program (not POSIX threads, which is beyond redemption) could insert > the relevant calls at the relevant places. With competent hardware > design, you could even get - heresy - checking! > > But I agree that what I was referring to was rather more ambitious > than what most other people may have been thinking of, despite the > fact that it IS the same issue, viewed in the large. BTW, explicit control of TLB is not impossible on the current generation of programs - most modern hardwares support enough features to make it possible (even if in a limited fashion) for system software to provide such a feature, although they are generally not implemented nor provided to the user level software in a generally useful form. -- #pragma ident "Seongbae Park, compiler, http://blogs.sun.com/seongbae/" .