Subj : Re: Using hierarchical memory as an acquire memory barrier for dependent To : comp.programming.threads,comp.arch From : nmm1 Date : Tue Sep 13 2005 08:35 am In article , David Hopwood wrote: >>> >>>The "something that isn't a performance bottleneck" was referring to >>>acquire memory barriers. Sorry if that wasn't clear. >> >> Ah. No, I didn't get that. >> >> However, my statement stands, even for those, though I don't see >> it that often. It is a major issue for OpenMP and POSIX threads >> codes that attempt to deliver small-grain parallelism. > >I don't think that the cost of acquire barriers, specifically, is the >cause of any performance problems with OpenMP and pthreads in providing >small-grain parallelism. Note that these barriers are almost certainly >not needed anyway on x86[-64], PPC or SPARC. Not acquire barriers in the very limited sense, no. But the logical extension of them from the ISA to the HLL interface. I agree that fiddling with the semantics to cure a hardware non-problem is not worth the bother, but doing to to address the very real problem I am referring to is. In particular, if you make cache and TLB control explicit, an OpenMP program (not POSIX threads, which is beyond redemption) could insert the relevant calls at the relevant places. With competent hardware design, you could even get - heresy - checking! But I agree that what I was referring to was rather more ambitious than what most other people may have been thinking of, despite the fact that it IS the same issue, viewed in the large. Regards, Nick Maclaren. .