Subj : Re: Using hierarchical memory as an acquire memory barrier for dependent To : comp.programming.threads,comp.arch From : David Hopwood Date : Tue Sep 13 2005 02:18 am Nick Maclaren wrote: > David Hopwood wrote: >>Nick Maclaren wrote: >> >>>|> Cache is supposed to be a transparent abstraction. So is the TLB (software >>>|> TLBs notwithstanding). Breaking that will break anyone's ability to understand >>>|> what the system is doing, just in order to try (without necessarily succeeding) >>>|> to optimize something that isn't a performance bottleneck. >>> >>>Don't be so certain of the last. I see both cache and TLB handling >>>being a performance bottleneck on a daily basis, and one of the >>>solutions to this would involve making them more visible. >> >>The "something that isn't a performance bottleneck" was referring to >>acquire memory barriers. Sorry if that wasn't clear. > > Ah. No, I didn't get that. > > However, my statement stands, even for those, though I don't see > it that often. It is a major issue for OpenMP and POSIX threads > codes that attempt to deliver small-grain parallelism. I don't think that the cost of acquire barriers, specifically, is the cause of any performance problems with OpenMP and pthreads in providing small-grain parallelism. Note that these barriers are almost certainly not needed anyway on x86[-64], PPC or SPARC. -- David Hopwood .