Subj : Re: Using hierarchical memory as an acquire memory barrier for
To   : comp.programming.threads,comp.arch
From : Alexander Terekhov
Date : Mon Sep 12 2005 08:06 pm


Joe Seigh wrote:
[...]
> I meant the specification.  

x86 loads from WB memory are loads ".acq" per specification of processor
consistency given in

http://research.compaq.com/wrl/people/kourosh/papers/1993-tr-68.pdf

I mean

http://groups.google.com/group/comp.programming.threads/msg/88755b3cd32f9f8c

regards,
alexander.

.