Subj : Re: Using hierarchical memory as an acquire memory barrier for dependent To : comp.programming.threads,comp.arch From : Joe Seigh Date : Mon Sep 12 2005 01:55 pm Sander Vesik wrote: > In comp.arch Nick Maclaren wrote: > >>In article , >>David Hopwood writes: >>|> >>|> Cache is supposed to be a transparent abstraction. So is the TLB (software >>|> TLBs notwithstanding). Breaking that will break anyone's ability to understand >>|> what the system is doing, just in order to try (without necessarily succeeding) >>|> to optimize something that isn't a performance bottleneck. >> >>Don't be so certain of the last. I see both cache and TLB handling >>being a performance bottleneck on a daily basis, and one of the >>solutions to this would involve making them more visible. > > > However, thats not what the original poster wanted to optimise - he > wanted to get some benefits for RCU by effectively breaking cache > transparency. > Nick is more correct. I was proposing it as a mechanism for preserving some of RCU's (or that of lock-free in general) performance if hardware was changed to improve its performance by relaxing some of the strict conditions it has to meet now. E.g. relaxing the cache protocols could improve performance by reducing cache invalidates if the de facto memory model did not require it. RCU was developed by Paul McKenney to allow in part, I think, better performance in a NUMA environment. If you exposed and possibly changed cache behavior in a so called UMA enviroment you could get some of the same benefits. -- Joe Seigh When you get lemons, you make lemonade. When you get hardware, you make software. .