Subj : Re: Using hierarchical memory as an acquire memory barrier for dependent  loads
To   : comp.programming.threads,comp.arch
From : Sander Vesik
Date : Mon Sep 12 2005 05:17 pm

In comp.arch Nick Maclaren <nmm1@cus.cam.ac.uk> wrote:
> 
> In article <wQ2Ve.21920$k22.1912@fe2.news.blueyonder.co.uk>,
> David Hopwood <david.nospam.hopwood@blueyonder.co.uk> writes:
> |> 
> |> Cache is supposed to be a transparent abstraction. So is the TLB (software
> |> TLBs notwithstanding). Breaking that will break anyone's ability to understand
> |> what the system is doing, just in order to try (without necessarily succeeding)
> |> to optimize something that isn't a performance bottleneck.
> 
> Don't be so certain of the last.  I see both cache and TLB handling
> being a performance bottleneck on a daily basis, and one of the
> solutions to this would involve making them more visible.

However, thats not what the original poster wanted to optimise - he 
wanted to get some benefits for RCU by effectively breaking cache 
transparency.

> 
> 
> Regards,
> Nick Maclaren.
> 
> 

-- 
	Sander

+++ Out of cheese error +++

.