Subj : Re: Using hierarchical memory as an acquire memory barrier for dependent
To   : comp.programming.threads,comp.arch
From : Joe Seigh
Date : Sun Sep 11 2005 08:39 pm

David Hopwood wrote:
> 
> Madness. Reading all that patent obfuscated English has addled your brain.

Some of the technical publications aren't any better. :)  Most of the patents
are on techniques published by the inventors.

> 
> Cache is supposed to be a transparent abstraction. So is the TLB (software
> TLBs notwithstanding). Breaking that will break anyone's ability to 
> understand
> what the system is doing, just in order to try (without necessarily 
> succeeding)
> to optimize something that isn't a performance bottleneck.
> 

You don't need it on most systems since they have dependent load ordering.
They're prefectly capable of running slow without any extra assistance.
But this would allow a more relaxed cache protocol / memory model to be
used that would allow improved hardware performance.  Anyway, after
the debacle with getting the x86 memory model semantics confused with its
implementation and attempts at hacks to improve global load ordering,
I would think everyone would be more attuned to the issue.  


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.