Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Sean Kelly
Date : Mon Sep 05 2005 10:45 am

Alexander Terekhov wrote:
> Alexander Terekhov wrote:
> [...]
> > Nah, loops are needed for LR-SC on Power. For x86, it is just a single
> > load followed by InterlockedCompareExchange(&addr, temp, temp) [MP
>
> Silly me. InterlockedCompareExchange(&addr, 42, 42) should work just
> fine. I've asked Andy Glew of Intel to confirm it ("Intel x86 memory
> model question" thread on comp.arch).

A load/store combination would definately work, but if CMPXCHG would
work as well then so much the better.  Is a separate load even
necessary then?  Assuming *addr != 42 then we've essentially loaded
addr twice in a row.


Sean

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