Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Sep 05 2005 03:25 pm


Alexander Terekhov wrote:
[...]
> Nah, loops are needed for LR-SC on Power. For x86, it is just a single
> load followed by InterlockedCompareExchange(&addr, temp, temp) [MP

Silly me. InterlockedCompareExchange(&addr, 42, 42) should work just
fine. I've asked Andy Glew of Intel to confirm it ("Intel x86 memory 
model question" thread on comp.arch).

> locked cmpxchg] ensuring WB-safe SC value for its result (and store-
> load fencing which is absent in PC).
> 
> >                            I just wonder why revised Java volatiles
> > (which supposedly meant to provide SC semantics) on x86 don't do that.
> 
> and don't do LR-SC loops on Power.

regards,
alexander.

.