Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Sep 05 2005 02:49 pm


Alexander Terekhov wrote:
[...]
> You can get classic SC under x86 PC if you replace all loads with
> load-cmpxchg-locked loops. 

Nah, loops are needed for LR-SC on Power. For x86, it is just a single
load followed by InterlockedCompareExchange(&addr, temp, temp) [MP
locked cmpxchg] ensuring WB-safe SC value for its result (and store-
load fencing which is absent in PC).

>                            I just wonder why revised Java volatiles
> (which supposedly meant to provide SC semantics) on x86 don't do that.

and don't do LR-SC loops on Power.

regards,
alexander.

.