Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Peter Dimov
Date : Sat Sep 03 2005 01:38 pm

David Hopwood wrote:
> Peter Dimov wrote:

> > x86 "in theory" or a currently shipping x86?
>
> Who knows? The fact that it can break in theory is enough for me.

In theory, you are right. In practice, if the weaker model has never
been deployed so far, doesn't provide a significant performance
improvement over TSO, and makes programs break in very subtle ways -
only on configurations with more than two CPUs, at that - it will never
occur in a shipping product.

> >>Andy Glew of Intel (sorta) confirmed that x86 is classic PC.
> >>
> >>http://groups.google.de/group/comp.arch/msg/7200ec152c8cca0c
> >
> > Very interesting. Doesn't this make atomic_load_acq and
> > atomic_store_rel... not very useful... on >2 CPU configurations? If
> > total order is impossible to achieve using atomics, how can one write
> > correct lock-free code?
>
> It's not impossible to achieve. It's just not achieved for that particular
> example. You can always add a StoreLoad barrier (using mfence) if you need
> it, but most lock-free stuff doesn't need it, because it doesn't rely on
> total store (or load) ordering.

I don't see how a StoreLoad can help. The example doesn't contain a
store followed by a load at all.

.