Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Sat Sep 03 2005 09:59 pm


David Hopwood wrote:
[...]
> >>http://groups.google.de/group/comp.arch/msg/7200ec152c8cca0c
> >
> > Very interesting. Doesn't this make atomic_load_acq and
> > atomic_store_rel... not very useful... on >2 CPU configurations? If
> > total order is impossible to achieve using atomics, how can one write
> > correct lock-free code?
> 
> It's not impossible to achieve. It's just not achieved for that particular
> example. You can always add a StoreLoad barrier (using mfence) if you need

Nope. Fencing has really nothing to do with "atomic visibility" ("a write 
becomes visible simultaneously to all processors other than the one that 
issued the write" -- Eric P.), aka  remote write atomicity. 

You'd have to use CAS or LR-SC (on power) to ensure causality.

http://tinyurl.com/83r9b

Constraint calculator:

http://tinyurl.com/9vamz

> it, but most lock-free stuff doesn't need it, because it doesn't rely on
> total store (or load) ordering.

Yep, most lock-free stuff doesn't rely on "atomic visibility" (remote
write atomicity).

regards,
alexander.

.