Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Peter Dimov
Date : Sat Sep 03 2005 12:20 pm

Alexander Terekhov wrote:
> Alexander Terekhov wrote:
> >
> > Peter Dimov wrote:
> > [...]
> > > I don't think that r1 == 0 && Y == 1 is possible on x86, which is
> > > basically the same model as SPARC-TSO (store buffering).
> >
> > Why does Intel call x86 model *processor consistency* (aka processor
> > ordering) and not TSO, then?
> >
> > > Is there a platform in existence that implements a variation of 'PC'
> > > that allows this outcome?
>
> x86.

x86 "in theory" or a currently shipping x86?

> > PC aside for a moment (lack of remote write atomicity is what
> > differentiates PC from TSO), it is widely reported in the literature
>
> Andy Glew of Intel (sorta) confirmed that x86 is classic PC.
>
> http://groups.google.de/group/comp.arch/msg/7200ec152c8cca0c

Very interesting. Doesn't this make atomic_load_acq and
atomic_store_rel... not very useful... on >2 CPU configurations? If
total order is impossible to achieve using atomics, how can one write
correct lock-free code?

.