Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads,comp.arch
From : Alexander Terekhov
Date : Sat Sep 03 2005 07:50 pm


Joe Seigh wrote:
[...]
> You seem to be assuming that the ia32 memory model is strictly just PC.
> I'm not assuming that and am *not* (for the zillionth time) talking about it
> in terms of a PC memory model.  If I was, I'd be wrong and you and Alexander
> would be correct.
> 
> If it turns out the ia32 memory model is just PC and all the extra statements
> about the memory model in the Intel docs is just noise then I'd be wrong and

SPO implementation details are irrelevant for reasoning program behaviour
under PC memory model. We are NOT talking about weakly-ordered WC stuff.

> again, you and Alexander would be right.  But so far *nobody* has clearly
> stated that.  I repeat, *nobody* has stated that.   Andy Glew has *not* stated
> that.  He has only spoken in terms of PC and not equivocated PC to the ia32
> memory model.  And if he doesn't do that then pretty much anything he says
> is irrelevant to the issue of what the ia32 memory model is.

He said "briefly stated: WB memory is processor consistent, type II."

With "type II" he meant Extension to Dubois’ Abstraction:

http://research.compaq.com/wrl/people/kourosh/papers/1993-tr-68.pdf

regards,
alexander.

.