Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Fri Sep 02 2005 12:18 pm


Peter Dimov wrote:
[...]
> I don't think that r1 == 0 && Y == 1 is possible on x86, which is
> basically the same model as SPARC-TSO (store buffering). 

Why does Intel call x86 model *processor consistency* (aka processor 
ordering) and not TSO, then?

> Is there a platform in existence that implements a variation of 'PC' 
> that allows this outcome?

PC aside for a moment (lack of remote write atomicity is what 
differentiates PC from TSO), it is widely reported in the literature 
that PowerPC lacks remote write atomicity. My understanding is that
sync/lwsync ensures that the next write (after fence) stalls until 
any updates or invalidates that have been issued on behalf of all 
previous writes (pror to fence) are acknowledged, but that doesn't 
preclude r1 == 0 && Y == 1 (in "single write" cases like that).

regards,
alexander.

P.S. http://tinyurl.com/83r9b

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