Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Chris Thomasson
Date : Thu Sep 01 2005 06:00 pm

> CPU1:
>
> st.rel X 1
> ld.acq Y
>
> CPU2:
>
> st.rel Y 1
> ld.acq X

The loads can migrate above the stores...

http://groups.google.com/group/comp.programming.threads/msg/68ba70e66d6b6ee9?hl=en




you need to do this:

st.rel 'location1'
mf
ld.acq 'location2'

in order to ensure the stores effects become visible before the subsequent 
ld.acq effects become applied.




> It is possible for CPU1 and CPU2 to both load 0.

Both of the loads could execute first. Remember:

The loads can migrate above the stores on IA32.

.