Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Peter Dimov
Date : Thu Sep 01 2005 03:17 pm

Seongbae Park wrote:

> > Under x86, r2 == r4 == 0 is still possible, because P1 and P2 are
> > allowed to observe the stores in a different order. There is no total
> > order on stores.
>
> Please see my other posting for one correct example
> to distinguish TSO and PC (hence store atomicity).

"If this PC is what I think it is[1], then following example would
distinguish
between PC and TSO:

Initially, X=Y=0
P1:  store 1,X
P2:  if (X==1) store 1,Y
P3:  if (Y==1) load X,r1

After executing this code,
r1==0 and Y==1 is possible on PC but not on TSO.
This is because P2 may see the store on P1 earlier than P3,
and P3 may see the store in P2 before it sees the store in P1."

I don't think that r1 == 0 && Y == 1 is possible on x86, which is
basically the same model as SPARC-TSO (store buffering). Is there a
platform in existence that implements a variation of 'PC' that allows
this outcome?

.