Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Thu Sep 01 2005 10:15 pm


Peter Dimov wrote:
[...]
> P1: st 1, X; ld X, r1; ld Y, r2
> P2: st 1, Y; ld Y, r3; ld X, r4
> 
> If the stores complete in an order that is the same for all processors,
> X,Y for example, then r4 must be 1. That's because r1 and r3 are
> obviously 1 (because of single thread constraints) and since the store
> of Y has been observed by P2, it follows that the store of X must be
> observed as well.
> 
> Under x86, r2 == r4 == 0 is still possible, because P1 and P2 are
> allowed to observe the stores in a different order. There is no total
> order on stores.

Such model (reads return values from memory and are not allowed to 
return values of pending writes from the store buffer) is called 
IBM-370, not TSO.

regards,
alexander

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