Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Thu Sep 01 2005 09:19 pm


Peter Dimov wrote:
[...]
> X = 0, Y = 0
> 
> CPU1:
> 
> st.rel X 1
> ld.acq Y
> 
> CPU2:
> 
> st.rel Y 1
> ld.acq X
> 
> It is possible for CPU1 and CPU2 to both load 0. This can't happen in a
> TSO model 

It can. 

TSO always allows a write followed by a read to complete out of program
order. All other program orders are maintained (together with "remote 
write atomicity").

regards,
alexander.

.