Subj : Re: Memory visibility and MS Interlocked instructions To : comp.programming.threads From : Seongbae Park Date : Thu Sep 01 2005 05:33 pm Alexander Terekhov wrote: > Correction... > > Alexander Terekhov wrote: >> >> Joe Seigh wrote: >> [...] >> > We're several posts out of sync here. When I said that I was thinking the >> > ia32 memory model as "defined" by the Itanium doc was equivalent to TSO. >> >> And that's wrong. > > But not absolutely. > >> >> > That is if all loads are ld.acq and all stores are st.rel then you effectively >> > get TSO. > > Only for WB memory. > > http://www.intel.com/design/itanium/downloads/25142901.pdf > > regards, > alexander. Thanks for the link. I was wondering what WB memory is, and you just made me read IA64 memory model spec :) BTW, for people not familiar with IA-64 (like me): WB memory == writeback. It's an attribute of memory that determines how IA-64 treats certain memory. There's four attributes - writeback, write-coalescing, uncacheable and uncacheable-exported. IA-64 defines store-releases to WB memory as globally ordered, so if you turn all load/store into load-aquire/store-release, you get TSO for all memory accesses to WB memory and PC for all memory accesses to WC memory. Now I can see another possible reason why it took so long for Intel to bring up Itanium - verification people would have hated this "collection of memory models". This WB memory is yet another confusing factor for people who's just trying to understand the memory model in general and IA-64 model in particular... No wonder this thread is extremely long. For anyone who's not following what Alexander has been talking about, I suggest at least the following two papers: Gharachorloo's 1990 ISCA paper on release consistency, and DEC WRL techreport 95/7 titled "Shared memory consistency models: a tutorial" by Adve and Gharachorloo. -- #pragma ident "Seongbae Park, compiler, http://blogs.sun.com/seongbae/" .