Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Thu Sep 01 2005 07:24 pm


Sean Kelly wrote:
[...]
>             If IA-32 stores do not "become remotely visible to all
> processors in the same order" then the assertion that all stores have

Frankly, I have no idea what they meant with these words in 3.3.7.1.

> release semantics is only true at a processor level, 

No. IA32 stores do (may) not become remotely visible atomically. 

That's it. 

3.3.7.1 has really nothing to do with release semantics.

You can get IA32/PC release semantics (i.e. without remote write 
atomicity) on IA64 by simply doing mf followed by unordered store.

It'll add a bit more constraints... but as far as you're concerned 
with "(REL)" and do not care about remote write atomicity "(WBR)", 
then 3.3.2 is the beef, not 3.3.7.1.

regards,
alexander.

.