Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Thu Sep 01 2005 02:29 pm

Correction...

Alexander Terekhov wrote:
> 
> Joe Seigh wrote:
> [...]
> > We're several posts out of sync here.  When I said that I was thinking the
> > ia32 memory model as "defined" by the Itanium doc was equivalent to TSO.
> 
> And that's wrong.

But not absolutely.

> 
> > That is if all loads are ld.acq and all stores are st.rel then you effectively
> > get TSO.

Only for WB memory.

http://www.intel.com/design/itanium/downloads/25142901.pdf

regards,
alexander.

.