Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Thu Sep 01 2005 11:52 am


Joe Seigh wrote:
[...]
> We're several posts out of sync here.  When I said that I was thinking the
> ia32 memory model as "defined" by the Itanium doc was equivalent to TSO.

And that's wrong.

> That is if all loads are ld.acq and all stores are st.rel then you effectively
> get TSO.  

Absolutely not.

regards,
alexander.

.