Subj : Re: Memory visibility and MS Interlocked instructions To : comp.programming.threads From : Joe Seigh Date : Wed Aug 31 2005 10:01 pm David Hopwood wrote: > Joe Seigh wrote: > >> Alexander Terekhov wrote: >> >>> David Hopwood wrote: >>> [...] >>> >>>> Yes, but PC alone does not imply load == load.acq. >>>> (I think; I'm not 100% sure.) >>> >>> >>> Heck, >>> >>> PC: >>> >>> (1) before a load access is allowed to perform with respect to any >>> other processor, all previous load accesses must be performed, and >>> >>> (2) before a store access is allowed to perform with respect to any >>> other processor, all previous load and store accesses must be performed. >>> >> >> You're making this up I think. > > > Huh? It's a direct quote from > . > It's not part of the standard PC definition. Not in the definitions that I googled and not in the definition in the Andy Glew posting and not in the definition in the ia32 manual. And while ia32 employs a read after write optimization, AFAIK it should be transparent to the memory model. And the ia32 manual definitely does not state the RAW optimization is the same as the one mentioned in that paper. So the side effects from the one in that paper may not apply to ia32 since we don't know what read after write implementation is used. But maybe I misunderstood what Alexander meant when he wrote "PC:" followed by two numbered bullets and thought he was trying to define processor consistency. -- Joe Seigh When you get lemons, you make lemonade. When you get hardware, you make software. .