Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Wed Aug 31 2005 09:15 pm

David Hopwood wrote:
> Alexander Terekhov wrote:
> 
>> Sean Kelly wrote:
>> [...]
>>
>>>> LFENCE or MFENCE depending on exact semantics desired.  That was until
>>>> I found out ia32 memory model is defined in the Itanium docs and it's
>>>> equivalent to Sparc TSO, loads are in order, etc...
>>>
>>>
>>> Understood.  This was mostly a theoretical question.
>>
>>
>> Joe still doesn't get it.
>> PC (load.acq/store.rel/...) != TSO. TSO is stricter than PC. PC is more
>> relaxed because it exposes "multiple-copy aspects of the memory" to 
>> the programmer. In this respect, PC is the same as RC and Power.
> 
> 
> I'm with Alexander here. TSO is definitely stricter.
> 
We're several posts out of sync here.  When I said that I was thinking the
ia32 memory model as "defined" by the Itanium doc was equivalent to TSO.
That is if all loads are ld.acq and all stores are st.rel then you effectively
get TSO.  I never said PC was equal to TSO.  The ia32 memory model isn't just
PC, it's other stuff in addition to it.  In fact you could probably subtract out
PC from ia32 and most of us would probably not notice it since we're not in general
doing anything that could depend on or exploit the partial ordering supplied
by PC.

But I am thinking now ia32 != TSO.  And of course plain PC != TSO.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.