Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : David Hopwood
Date : Wed Aug 31 2005 11:53 pm

Alexander Terekhov wrote:
> David Hopwood wrote:
>>Joe Seigh wrote:
>>
>>>If you're thinking that doesn't matter because processor consistency
>>>gives you release and acquire semantics between two processors.  But
>>>what if you have 3 (or more) processors?   For example, processor A
>>>initializes and stores its address in X.   Processors B reads X.  So
>>>far, so good.  All the stores by A are read in proper order by B.
>>>Now processors B stores the object address in Y and processor C reads Y.
>>>Now there's a problem.  There's no guarantee that processor C will see
>>>the writes by A in proper order (i.e. relative to the read of Y).  So
>>>processor consistency doesn't give you acquire and release as they are
>>>commonly understood.
>>
>>Right. 
> 
> Wrong.

You're absolutely correct. I had misunderstood the definition of PC.

>      if (u != null && u->foo != 1) { !! broken PC hardware check
>        turn_on_sirens();
>        halt();
>      }

I believe the traditional instruction is halt_and_catch_fire().

-- 
David Hopwood <david.nospam.hopwood@blueyonder.co.uk>

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