Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Wed Aug 31 2005 10:05 pm


David Hopwood wrote:
[...]
> Yes, but PC alone does not imply load == load.acq.
> (I think; I'm not 100% sure.)

Heck,

PC:

(1) before a load access is allowed to perform with respect to any 
other processor, all previous load accesses must be performed, and

(2) before a store access is allowed to perform with respect to any 
other processor, all previous load and store accesses must be 
performed.

RC (without nsync):

(1) before an acquire access or an ordinary access is allowed to 
perform with respect to any other processor, all previous acquire 
accesses must be performed, and 

(2) before a release access is allowed to perform with respect to 
any other processor, all previous acquire accesses, release 
accesses, and all ordinary accesses must be performed. 

Now, let's make acquire := load.acq, release := store.rel, and 
ordinary := nonexistent, so that we can get...

Totally Castrated RC:

(1) before a load.acq access or a nonexistent access is allowed to 
perform with respect to any other processor, all previous load.acq 
accesses must be performed, and 

(2) before a store.rel access is allowed to perform with respect to 
any other processor, all previous load.acq access, store.rel 
accesses, and all nonexistent accesses must be performed.

Let's clean it up.

(1) before a load.acq access is allowed to perform with respect to 
any other processor, all previous load.acq accesses must be 
performed, and 

(2) before a store.rel access is allowed to perform with respect 
to any other processor, all previous load.acq and store.rel 
accesses must be performed. 

Now compare it with the PC above.

regards,
alexander.

.