Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Wed Aug 31 2005 08:09 pm


Sean Kelly wrote:
[...]
> > LFENCE or MFENCE depending on exact semantics desired.  That was until
> > I found out ia32 memory model is defined in the Itanium docs and it's
> > equivalent to Sparc TSO, loads are in order, etc...
> 
> Understood.  This was mostly a theoretical question.

Joe still doesn't get it. 

PC (load.acq/store.rel/...) != TSO. TSO is stricter than PC. PC is more
relaxed because it exposes "multiple-copy aspects of the memory" to the 
programmer. In this respect, PC is the same as RC and Power.

regards,
alexander.

.