Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Sean Kelly
Date : Wed Aug 31 2005 10:30 am

Joe Seigh wrote:
> Sean Kelly wrote:
> >
> > Out of curiosity, how would you write code to handle this model for
> > x86?  Use LOCK on loads as well?
> >
> >
> LFENCE or MFENCE depending on exact semantics desired.  That was until
> I found out ia32 memory model is defined in the Itanium docs and it's
> equivalent to Sparc TSO, loads are in order, etc...

Understood.  This was mostly a theoretical question.

> I don't know what the PC model is about but it has nothing to do with
> the memory model as viewed by the programmer.  Same for speculative loads,
> write combining, etc...  SSE and string memory accesses are the exception
> to the TSO memory model, they're out of order, but who cares why they're
> out of order.

Yup.  I think I have a pretty good grasp of the differences between PC
and the memory model thanks to this thread, though I suppose a bit more
research on this aspect of computer architecture couldn't hurt :)
Thanks!


Sean

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