Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : David Hopwood
Date : Wed Aug 31 2005 05:20 pm

Joe Seigh wrote:
> If you're thinking that doesn't matter because processor consistency
> gives you release and acquire semantics between two processors.  But
> what if you have 3 (or more) processors?   For example, processor A
> initializes and stores its address in X.   Processors B reads X.  So
> far, so good.  All the stores by A are read in proper order by B.
> Now processors B stores the object address in Y and processor C reads Y.
> Now there's a problem.  There's no guarantee that processor C will see
> the writes by A in proper order (i.e. relative to the read of Y).  So
> processor consistency doesn't give you acquire and release as they are
> commonly understood.

Right. In the x86 model:

Start with object.foo == 0, X == null.

Processor A:
   object.foo := 1
   // implicit release [*]
   X := &object
   // implicit release

Processor B:
   // implicit acquire
   t := X
   Y := t
   // implicit release

Processor C:
   // implicit acquire
   u := Y
   // implicit acquire [**]
   if (u != null) then v := u->foo else v := 1


If Alexander is correct about the implicit load.acq and store.rel on x86,
then [*] and [**] ensure that v != 0. This is indeed stronger than processor
consistency; processor consistency alone does not guarantee that C will not
see v == 0. But x86 apparently does (or so it would seem from reading the
Itanic manuals).

-- 
David Hopwood <david.nospam.hopwood@blueyonder.co.uk>

.