Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Wed Aug 31 2005 01:17 pm

Sean Kelly wrote:
> Joe Seigh wrote:
> 
>>Anyway, we're *not* talking about release consistency.  We're talking
>>about whether PC implies loads (not stores) are in order or not.  I
>>provided a counter example to the in-order theory.
>>
>>I'm going to stick with the loads are out-of-order model.
> 
> 
> Out of curiosity, how would you write code to handle this model for
> x86?  Use LOCK on loads as well?
> 
> 
LFENCE or MFENCE depending on exact semantics desired.  That was until
I found out ia32 memory model is defined in the Itanium docs and it's
equivalent to Sparc TSO, loads are in order, etc...

I don't know what the PC model is about but it has nothing to do with
the memory model as viewed by the programmer.  Same for speculative loads,
write combining, etc...  SSE and string memory accesses are the exception
to the TSO memory model, they're out of order, but who cares why they're
out of order.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.