Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Mayan Moudgill
Date : Wed Aug 31 2005 12:45 pm

Alexander Terekhov wrote:
> Mayan Moudgill wrote:
> [...]
> 
>>>X,Y,Z are initially 0.
>>>processor 1 writes X with 42.
>>>processor 1 writes Y with 2.
>>>processor 2 reads 2 from Y and writes Z with that value.
>>>processor 3 reads 2 from Z and 0 from X.
>>
>>Yes, that is also possible. 
> 
> 
> No. Under PC, what processor1 did is equivalent to
> 
> processor 1 writes X with 42.
> processor 1 executes SFENCE.
> processor 1 writes Y with 2.
> 
> What you seem to have in mind would make SFENCE (and MFENCE regarding 
> stores) pretty useless. 
> 
> regards,
> alexander.

I don't think its relevant (to Joe Seigh at least) what processor 
consistency would (or would not) imply. What's important is what is 
implied by the *x86* memory model.

If the example above is not possible under processor consistency, then 
the following are possible:
1. x86s are not using PC OR
2. andy glew is wrong.

I would pick option #1, given that Andy Glew definitely had a major hand 
in defining the memory model.

.