Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Wed Aug 31 2005 06:06 pm


Mayan Moudgill wrote:
[...]
> > X,Y,Z are initially 0.
> > processor 1 writes X with 42.
> > processor 1 writes Y with 2.
> > processor 2 reads 2 from Y and writes Z with that value.
> > processor 3 reads 2 from Z and 0 from X.
> 
> Yes, that is also possible. 

No. Under PC, what processor1 did is equivalent to

processor 1 writes X with 42.
processor 1 executes SFENCE.
processor 1 writes Y with 2.

What you seem to have in mind would make SFENCE (and MFENCE regarding 
stores) pretty useless. 

regards,
alexander.

.