Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Mayan Moudgill
Date : Wed Aug 31 2005 11:26 am

Alexander Terekhov wrote:
> Mayan Moudgill wrote:
> [...]
> 
>>Having looked at Andy's answer, it appears that the following is possible:
>>
>>Y,Z are initially 0.
>>processor 1 writes Y with 2.
>>processor 2 reads 2 from Y and writes Z with that value.
>>processor 3 reads 2 from Z and 0 from Y.
>>
>>This is the "obvious" behavior assuming a processor with in-order stores
>>(via a store buffer) using ...
> 
> 
> Sure. 
> 
> Contrast it with (that's what I thought Joe was driving at when he 
> alleged that PC is somewhat more relaxed than RC... I mean his claim
> that "processor consistency doesn't give you acquire and release as 
> they are commonly understood"):
> 
> X,Y,Z are initially 0.
> processor 1 writes X with 42.
> processor 1 writes Y with 2.
> processor 2 reads 2 from Y and writes Z with that value.
> processor 3 reads 2 from Z and 0 from X.

Yes, that is also possible. Roughly, here is how it could work:

p1 writes X,Y
    p3 gets msgs from p1 say "I have updated X,Y"
p2 copies Y to Z
    p3 gets msg from p2 saying "I have updated Z"
p3 now reads X,Z
    p3 gets msg from p2 saying "I have updated X,Y"

Note that the following conditions are maintained:
- both p2 and p3 see the writes from p1 in the same order
- p3 and p2 observes writes from p1,p2 in a different order from each other.

This is completely consistent with the following:
http://groups.google.com/group/comp.arch/msg/96ec4a9fb75389a2

> In a multiprocessor system, the following rules apply:
> * Individual processors obey the same rules as in a single
>    processor system.
> * Writes by a single processor are observed in the same
>    order by all other processors.
> * Writes by different processors on the system bus [*gack*]
>    are NOT observed by processors in the same order.>>

This is exactly what could happen on an MP system with some kinds of 
interconnects other than shared buses.

The fact remains, of course, that as long as you're working with a 
single bus and processors that have MESI, then the *actual* behavior is 
what you expect (writes by different processors are observed by all 
processors in the same order).

But that is not what the *model* allows for (at least according to Andy 
Glew). So I am inclined to believe that Joe Seigh is correct about the 
actual memory model used by the x86.

.