Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Wed Aug 31 2005 09:07 am

Joe Seigh wrote:
> 
> Now if this can be reconciled with AMD's
>  Out-of-order reads are allowed. Out-of-order reads can occur
>  as a result of out-of-order instruction execution or
>  speculative execution. The processor can read memory outof-
>  order to allow out-of-order execution to proceed.
> 
> 
I am guessing AMD's memory model is the same as Intel's for ia32
and ia32-64.  If it was a weaker memory model then you couldn't
run programs written for Intel processors on AMD processors, but
programs written for AMD processors could run on Intel processors,
which wouldn't make a lot of business sense for AMD.  And it
doesn't make a lot of sense for them to have changed the memory
model when they created ia32-64 since ia32 is a subset of it.

-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.