Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Mayan Moudgill
Date : Tue Aug 30 2005 11:46 pm

Alexander Terekhov wrote:
> Mayan Moudgill wrote:
> [...]
> 
>>Ask in comp.arch, 
> 
> 
> Joe Seigh did it already.
> 
> http://groups.google.com/group/comp.arch/msg/9e507575af908132
> 
> 
> 
>>                  people like Andy Glew and others might be able to give 
>>a reasonably authoritative answer.
> 
> 
> Andy Glew did it already.
> 
> http://groups.google.com/group/comp.arch/msg/96ec4a9fb75389a2
> 
> regards,
> alexander.

Having looked at Andy's answer, it appears that the following is possible:

Y,Z are initially 0.
processor 1 writes Y with 2.
processor 2 reads 2 from Y and writes Z with that value.
processor 3 reads 2 from Z and 0 from Y.

This is the "obvious" behavior assuming a processor with in-order stores 
(via a store buffer) using a non-broadcast interconnect.

.