Subj : Re: Memory visibility and MS Interlocked instructions To : comp.programming.threads From : David Hopwood Date : Wed Aug 31 2005 02:31 am Joe Seigh wrote: > David Hopwood wrote: >> Joe Seigh wrote: >> >>> We're talking about whether PC implies loads (not stores) are in >>> order or not. >> >> I don't even know what "loads are in order" would mean. What Alexander >> was claiming was that on x86 load implies load.acq. This *is* consistent with >> what the P4 manual says, insofar as the manual makes sense. > > Memory barriers order access w.r.t. memory. "loads in order" means > #LoadLoad between loads. In that case, I'm currently working on the assumption that loads *are* "in order" on x86 (ignoring weak memory types etc.) Why do you think that your example demonstrates otherwise? > I'm not sure what you think "out-of-order" means then. I don't find that to be a sensible way to describe memory models (as opposed to implementations). I tend to model shared memory in terms of message passing, i.e. a load is modelled as a message from the memory (or cache in a non-cache-coherent system) to the processor, and the "out of order" aspect corresponds to the fact that messages may cross. But YMMV; I do it that way because I'm more familiar with message passing models (which are generally simpler). -- David Hopwood .