Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Wed Aug 31 2005 03:19 am


Alexander Terekhov wrote:
> 
> Joe Seigh wrote:
> >
> > Alexander Terekhov wrote:
> > > Joe Seigh wrote:
> > > [...]
> > >
> > >>If Andy had simply stated that loads were in order ...
> > >
> > >
> > > Once again: please show some pseudo code with *FENCE (or whatever) that
> > > you think is required to ensure visibility of some object initialized
> > > and published by A (OBJECT = ..., ptr1 = &OBJECT) to C (object = *ptr2)
> > > after republishing it by B (r = ptr1, ptr2 = r).
> > >
> > > regards,
> > > alexander.
> >
> > Well, the corrected version of the sample I posted to c.a. ...
> 
> So you have only one store performed by A, and your (corrected) beef is
> about allowing B to perform a load yielding the value of A's store{.rel})
                                    ^
                                    |
{.acq} -----------------------------+

> before A's store is made visible to all other processors. It's the same
                  ^
                  |
{.rel} -----------+

> behavior as under release consistency... and your lovely PPC works that
> way too.

On Power, naked LR-SC "validated reads" (on both B and C; instead of load
{.acq}) can be used to inhibit that relaxation.

regards,
alexander.

.