Subj : Re: Memory visibility and MS Interlocked instructions To : comp.programming.threads From : David Hopwood Date : Wed Aug 31 2005 01:07 am Joe Seigh wrote: > David Hopwood wrote: > >> You may be confused by: >> >> # Writes by a single processor are observed in the same order by all >> # processors. >> >> (from section 7.2.1 of vol. 3 of the P4 arch manual). This is >> *incorrect*. >> It should say "Writes by a single processor are observed in the same >> order by all _other_ processors." Otherwise it would be inconsistent with >> point 6 earlier in the same section. > [...] > Point 6 is that store followed by a load "as if" optimization. It's not an "as if" optimization: remember that a processor can cause side- effects other than stores. It can therefore signal that it has already seen the effect of a store, before other processors could have seen that effect. If *all* side-effects went through the same buffer then it would be an "as if" optimization. -- David Hopwood .