Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Tue Aug 30 2005 08:12 pm

David Hopwood wrote:
> Joe Seigh wrote:
> 
>> Alexander Terekhov wrote:
>>
>>> Alexander Terekhov wrote:
>>>
>>>> Andy Glew did it already.
>>>>
>>>> http://groups.google.com/group/comp.arch/msg/96ec4a9fb75389a2
>>>
>>>
>>> And even Mike Haertel did it already.
>>>
>>> http://groups.google.com/group/comp.arch/msg/8d074f7eb0be914d
>>>
>>> (that's apart from http://www.well.com/~aleks/CompOsPlan9/0005.html)
>>
>>
>> Yes, well PC will give you TSO for two processors per Mike's example.
> 
> 
> No. Remember that loads may be satisfied from the store buffer of the
> same processor, in a different order than the other processor sees them.
> That is not allowed by TSO.
> 
> You may be confused by:
> 
> # Writes by a single processor are observed in the same order by all
> # processors.
> 
> (from section 7.2.1 of vol. 3 of the P4 arch manual). This is *incorrect*.
> It should say "Writes by a single processor are observed in the same
> order by all _other_ processors." Otherwise it would be inconsistent with
> point 6 earlier in the same section.
> 

Right.  2 processors with PC won't give you TSO.  I was thinking in terms
of 3 processors and not trying to come up with a 2 processor counter example
which is pretty easy now that I think of it.

processor 1:       store X; load X; load Y;
processor 2:       store Y; load Y; load X;

TSO would require that both processors don't see the old value stored
by the other processor.  PC doesn't requiere that.

Point 6 is that store followed by a load "as if" optimization.  It's subject to
PC definition contraints.

-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.