Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Tue Aug 30 2005 06:50 pm

Alexander Terekhov wrote:
> Joe Seigh wrote:
> [...]
> 
>>If Andy had simply stated that loads were in order ...
> 
> 
> Once again: please show some pseudo code with *FENCE (or whatever) that 
> you think is required to ensure visibility of some object initialized 
> and published by A (OBJECT = ..., ptr1 = &OBJECT) to C (object = *ptr2) 
> after republishing it by B (r = ptr1, ptr2 = r). 
> 
> regards,
> alexander.

Well, the corrected version of the sample I posted to c.a.

=
processor 1 stores into X
processor 2 see the store by 1 into X and stores into Y

So the store into Y occurred after causal reasoning.

processor 3 loads from Y
processor 3 loads from X

If loads were in order you could infer that if processor 3
sees the new value of Y then it will see the new value of X.
But the rules for processor consistency *clearly* state that
you will not necessarily see stores by different processors in
order.
=

LFENCE doesn't really work with a pure processor consistency
definition.   It has to be defined in terms of memory order
(PC doesn't mention memory and doesn't require memory).  The
other parts of the x86 memory model are defined this way, i.e.
stores are in order.

-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.