Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Tue Aug 30 2005 05:50 pm

Sean Kelly wrote:
> 
>>From what Alex has been saying, it seems like loads may occur out of
> order at a hardware level, but because of the PC model they appear to
> occur in order at the program level.  Assuming this is true, all the
> talk of behavior at the system bus level is a red herring, as while it
> may actualy be taking place, it's not something we need to worry about.
>  The resonse from Andy seems to confirm this:
> 
> - It was necessary to mention this because validation folk, usually
> - fresh out of college, would write a test, see a load on the bus
> - occurring before an older store, and think they had discovered a bug.
> - Ditto posters to comp.arch.
> 
> It's somewhat unfortunate that the spec used for internal validation is
> apparently the same one Intel released for public consumption, though I
> suppose there's no practical way around it.
> 
> 
PC model does not infer loads are in order.  And yes, speculative loads
are a red herring.  They don't affect the load ordering since you can
have speculative loads with either memory model.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.